Controllable latch/register circuit
US6265922A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A controllable latch/register circuit for an integrated circuit comprises an input latch (30) coupled in series with an output latch (32). The latches are operated under control of a control circuit (34) having mode inputs. In one mode, the latches are operated as a non-transparent register; the output latch (32) holds the output stable while new data is inputted to the input latch (30); the output latch (32) is only opened once the input latch has been latched closed. In one or more other modes, the latches are operated as a single controllable transparent latch; for example, one or the latches (30) can be held permanently open such that operation of the circuit depends entirely on the state of the other latch (32). Applications include dual purpose interface circuits for synchronous and asynchronous memories, and configurable circuits operable as high speed latches during normal operation, and as scan-test registers during a scan-test operation, thus avoiding the problems of dedicated latch-only and register-only circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.