Graham Kirsch
63Patents
12h-index
13Co-inventors
81Inventor score
Filing activity: Dec 13, 1996 → Nov 13, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6785780B1 | Distributed processor memory module and method | Physics | 108 | Expired |
| US6574590B1 | Microprocessor development systems | Physics | 66 | Expired |
| US6385742B1 | Microprocessor debugging mechanism employing scan interface | Physics | 65 | Expired |
| US8411998B2 | Method and apparatus providing perspective correction and/or image dewarping | Physics | 28 | Active |
| US8712162B2 | Interest point detection | Physics | 22 | Active |
| US6754802B1 | Single instruction multiple data massively parallel processor systems on a chip and system using same | Physics | 19 | Expired |
| US5987239A | Computer system and method for building a hardware description language representation of control logic for a complex digital system | Physics | 16 | Expired |
| US8797387B2 | Self calibrating stereo camera | Physics | 15 | Active |
| US7107412B2 | Distributed processor memory module and method | Physics | 14 | Expired |
| US7283080B2 | High density row RAM for column parallel CMOS image sensors | Electricity | 14 | Expired |
| US7181593B2 | Active memory command engine and method | Physics | 13 | Expired |
| US7584343B2 | Data reordering processor and method for use in an active memory device | Physics | 13 | Active |
| US7454593B2 | Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect | Physics | 12 | Expired |
| US6473727B1 | Processor development systems | Physics | 10 | Expired |
| US6265922A | Controllable latch/register circuit | Physics | 10 | Expired |
| US7069416B2 | Method for forming a single instruction multiple data massively parallel processor system on a chip | Physics | 8 | Expired |
| US6754801B1 | Method and apparatus for a shift register based interconnection for a massively parallel processor array | Physics | 8 | Expired |
| US6788613B1 | Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface | Physics | 7 | Expired |
| US7073039B2 | Providing a register file memory with local addressing in a SIMD parallel processor | Physics | 7 | Expired |
| US7149875B2 | Data reordering processor and method for use in an active memory device | Physics | 6 | Expired |
| US7386689B2 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner | Physics | 6 | Expired |
| US7073034B2 | System and method for encoding processing element commands in an active memory device | Physics | 5 | Expired |
| US7830292B2 | High density row RAM for column parallel CMOS image sensors | Electricity | 5 | Active |
| US6981012B2 | Method and circuit for normalization of floating point significants in a SIMD array MPP | Physics | 3 | Expired |
| US9013615B2 | Image sensor with flexible interconnect capabilities | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.