ESD protection network for circuit structures formed in a semiconductor

US6266222A · kind A · utility

Assignee

• STMicroelectronics SA

Inventors

• Paolo Colombo · Padova, IT
• Jacopo Mulatti · Bibione, IT
• Roberto Annunziata · Monza, IT
• Giovanni Campardo · Bergamo, IT
• Marco Maccarrone · Palestro, IT

Key dates

• Filing date: Dec 30, 1998
• Grant date: Jul 24, 2001
• Expiry date: Dec 30, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.