Method of operating a memory device having write latency
US6266285A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operation of a memory device. The memory device including a section of memory having a plurality of memory cells. The method of operation comprises receiving a request for a write operation and sampling a first portion of data after a delay time transpires in response to the request for a write operation. A method of controlling the memory device comprises issuing a request for a write operation to the memory device. The memory device samples data after a number of clock cycles of the external clock signal transpire in response to the request. The method of controlling also comprises issuing a first portion of data to the memory device after the number of clock cycles of the external clock signal transpire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.