High speed four-to-two carry save adder
US6266757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1998 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | May 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3555
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for adding two or more numbers and generating a sum and carry output is disclosed. The adder circuit receives two or more numbers to be added together. The adder circuit includes a number of exclusive-or logic circuits that generate intermediate outputs. The intermediate outputs are input to a domino multiplexer. The domino multiplexer includes a multiplexer gate and an exclusive-or gate connected in parallel. The domino multiplexer circuit outputs a sum value and a carry value for the input numbers. A clock signal drives the multiplexer gate and the exclusive-or gate in the domino multiplexer circuit. This clock signal synchronizes the input of the numbers to be added together and the addition operation in the domino multiplexer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.