Split transaction I/O bus with pre-specified timing protocols to synchronously transmit packets between devices over multiple cycles
US6266778A · kind A · utility
14Cited by
38References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.