Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry
US6268274A · kind A · utility
10Cited by
17References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Oct 14, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/937
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.