Method of forming wirings
US6268290A · kind A · utility
9Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 1994 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | May 27, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming wirings which comprises forming a film of a silicon-containing metal layer at a high temperature on an underlying metals, thereby forming a silicon alloy layer comprising the underlying metal and the silicon-containing metal during film formation. In a case of forming wirings by a silicon-containing metal layer occurrence of Si nodules can be eliminated to obtain wirings of high reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.