Low temperature process for multiple voltage devices
US6268296A · kind A · utility
30Cited by
12References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Dec 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/022
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface. Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30). The entire wafer (10) is exposed to a nitrogen ion containing plasma to form a nitrided layer (22). The photoresist (14) is removed, and the exposed portion of the oxide layer (12) is etched to the wafer (10) surface. Finally, an oxidation step forms a silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.