Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces
US6268297A · kind A · utility
8Cited by
3References
15Claims
0Family size
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Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.