Vertical channel field effect transistor
US6268621A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Aug 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the bottom terminal, the channel, and the top terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.