Method for manufacturing flash memory device with dual floating gates and two bits per cell
US6271090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method for manufacturing a flash memory device with dual floating gates is disclosed. The method use a self-align etching technique to form dual floating gates by using dual spacers as masks. First of all, a semiconductor substrate having a first insulating layer thereon and a first conductive layer formed over the first insulating layer is provided. Then a second insulating layer is formed and patterned to etch to form a trench therein. Next a dielectric layer is deposited and anisotropically etched to form dual spacers in the trench. After removing the second insulating layer, etching the first conductive layer to expose the first insulating layer, and removing the spacers sequentially, dual floating gates are formed. Two doped regions separately located on two sides of said dual floating gates are then formed by using a photolithography and an ion implantation processes After thickening the first insulating layer, a composite layer, a second conductive layer and a third insulating layer is formed over the semiconductor substrate sequentially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.