Twin-cell memory architecture with shielded bitlines for embedded memory applications
US6272054A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Oct 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A twin cell memory array which includes shielded bitlines is provided. The twin cell memory array includes a plurality of bitlines arranged in one direction in parallel with each other, with every other bitline constituting a bitline pair; a plurality of sense amplifiers being arranged in a line, wherein each sense amplifier is interconnected to two adjacent bitline pairs; a plurality of wordlines arranged in a direction intersecting said plurality of bitlines, wherein a single wordline is coupled to every other bitline; and isolation means located on said plurality of bitlines, said isolation means being arranged such that when every other bitline of said plurality of bitlines is being sensed, the adjacent bitlines of said plurality of bitlines are held at a predetermined potential by a clamping means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.