Semiconductor memory with programmable bitline multiplexers
US6272062A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | May 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.