Method and apparatus for built-in self-test of logic circuitry
US6272653A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention comprises a method and apparatus for built-in self-test of logic circuitry for logic under test. The logic under test comprises a plurality of test points, each test point having a plurality of nodes. The test circuitry comprises a linear finite state machine. The linear finite state machine generates subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine. Moreover, the contents of the linear finite state machine are readable or writable via scan. The preferred implementation also comprises a test data bus coupled between the logic under test and the linear finite state machine. The test data bus is configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.