Method of reducing test time for NVM cell-based FPGA

US6272655A · kind A · utility

Assignee

• Actel Corporation · US

Inventors

• Volker Hecht · Barsinghausen, DE
• Timothy Saxe · Ramona, US

Key dates

• Filing date: Jun 11, 1998
• Grant date: Aug 7, 2001
• Expiry date: Jun 11, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318519
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The present invention provides for a method of testing an FPGA using NVM memory cells for programmable interconnects. The NVM memory cells are arranged as a memory array of rows and columns. User-configurable logic elements and interconnections, which are programmed by the stored states of the memory cells, are organized into identical and/or differing tiles. The tiles are organized into an array of rows and columns superimposed upon the memory array. The testing method includes: selecting test circuit configurations by which identical tiles are identically programmed as much as possible; and simultaneously programming and simultaneously erasing pluralities of the memory rows corresponding to the tiles into the test circuit configurations. Additionally, the test circuit configurations programmed into the FPGA are tested at a lower supply voltage than that of normal operation. Programming is performed at reduced programming and erasing pulse voltages and times by substantially ignoring retention and disturb effect margin amounts for the NVM memory cells. In this manner, the time for testing the FPGA is considerably reduced.