Annealing of a crystalline perovskite ferroelectric cell
US6274388A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a ferroelectric capacitor usable as a memory cell in a non-volatile integrated circuit memory integrated on a silicon substrate, preferably including an intermetallic barrier layer. The memory cell consists of a ferroelectric layer, for example of lead niobium zirconium titanate (PNZT) sandwiched between metal oxide electrodes, for example of lanthanum strontium cobaltite (LSCO), which forms with a crystalline orientation and provides a growth template for the crystalline formation of the ferroelectric. The intermetallic layer prevents diffusion of oxygen from the bottom LSCO electrode down to the underlying silicon. At least the bottom electrode is subjected to a rapid thernal anneal at an annealing temperature above its growth temperature. Thereby, the polarization and fatigue characteristics of the ferroelectric cell are improved. Also, a similar intermetallic layer may be placed above the ferroelectric cell. A preferred composition of the intermetallic layer is a refractory silicide, especially a refractory disilicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.