Process sequence to improve DRAM data retention
US6274481A · kind A · utility
1Cited by
8References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The sidewall nitride etch is modified to leave a thin layer of nitride covering the silicon in a DRAM array. The nitride layer prevents damage to the silicon and improves the integrity and refresh time of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.