Semiconductor device and manufacturing method therefor
US6274887A · kind A · utility
507Cited by
14References
81Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 1, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/3026
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.