Integrated circuit diode, and method for fabricating same
US6274918A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Feb 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
An integrated circuit (10) includes a P-epi substrate (12) having therein an n-well isolation layer (13) and a p-well (14) within the n-well. The p-well includes adjacent an upper surface thereof a p+ layer (18) having several elongate parallel openings (21-23) therethrough. Each of the openings has therein a respective n- RESURF layer (26-28). Each n- RESURF layer has therethrough a respective further elongate opening (31-33), and has a uniform horizontal thickness all around that opening. Each of the openings in the RESURF layers has therein an n+ finger (36-38). The p+ layer and the n+ fingers each have a vertical thickness which is greater than the vertical thickness of the n- RESURF layers. The p+ layer serves as the anode of a zener diode, and the n+ fingers are interconnected and serve as the cathode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.