Integrated circuit device having a planar interlevel dielectric layer
US6274933A · kind A · utility
10Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Aug 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a conductive layer adjacent a semiconductor substrate. The conductive layer includes conductive lines having gaps therebetween. A fluoro-silicate glass (FSG) layer is over the patterned conductive layer fills the gaps between conductive lines. Also, an undoped oxide layer is on the FSG layer. Peaks of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.