Data input/output system for multiple data rate memory devices
US6275441A · kind A · utility
19Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jun 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuitry for implementing memory devices with I/O architectures that transmit multiple data bits on a data I/O interconnect line during a single clock cycle. Instead of increasing the physical number of I/O interconnect lines to match the increased number of data bits being processed by the multiple data rate memory circuit, a time sharing scheme is devised that processes the multiple bits of data with a minimum number of I/O lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.