G-Link Technology
12Patents
0Active
12Granted
28Portfolio score
Filing activity: Jun 3, 1998 → Mar 18, 2004
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6765976B1 | Delay-locked loop for differential clock signals | Electricity | 39 | Expired |
| US6275441A | Data input/output system for multiple data rate memory devices | Physics | 19 | Expired |
| US6606272B2 | Method and circuit for processing output data in pipelined circuits | Physics | 9 | Expired |
| US6031784A | Hierarchical decoding of a memory device | Physics | 9 | Expired |
| US5970020A | Controlling the set up of a memory address | Physics | 8 | Expired |
| US6033945A | Multiple equilibration circuits for a single bit line | Emerging Cross-Sectional Technologies | 7 | Expired |
| US6166976A | Multiple equilibration circuits for a single bit line | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6529428B2 | Multi-bit parallel testing for memory devices | Physics | 3 | Expired |
| US7027344B1 | High-speed semiconductor memory having internal refresh control | Physics | 2 | Expired |
| US6154386A | Memory device having a wide data path | Physics | 1 | Expired |
| US6501670B1 | High speed memory architecture and busing | Physics | 0 | Expired |
| US6445641B1 | Memory device with time shared data lines | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.