Method and apparatus for an enhanced floating point unit with graphics and integer capabilities
US6275838A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Oct 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced floating point unit that supports floating point, integer, and graphics operations by combining the units into a single functional unit is disclosed. The enhanced floating point unit comprises a register file coupled to a plurality of bypass multiplexers. Coupled to the bypass multiplexers are an aligner and a multiplier. And, coupled to the multiplier is an adder that further couples to a normalizer/rounder unit. The normalizer/rounder unit may comprise a normalizer and a rounder coupled in series and or a parallel normalizer/rounder. The enhanced floating point unit supports both integer operations and graphics operations with one functional unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.