System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time
US6275924A · kind A · utility
3Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the invention, a method of buffering instructions in a processor having a pipeline having a decode stage includes detecting stalling of the decode stage, reissuing a previous fetch for an instruction in a memory until the decode stage is no longer stalled, and writing the fetch instruction into an instruction buffer after the decode stage is no longer stalled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.