Deepak Mital
26Patents
6h-index
21Co-inventors
69Inventor score
Filing activity: Sep 15, 1998 → Mar 12, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8321385B2 | Hash processing in a network communications processor architecture | Electricity | 33 | Active |
| US8515965B2 | Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors | Electricity | 18 | Active |
| US8407707B2 | Task queuing in a network communications processor architecture | Electricity | 9 | Active |
| US8949838B2 | Multi-threaded processing with hardware accelerators | Electricity | 7 | Active |
| US9152564B2 | Early cache eviction in a multi-flow network processor architecture | Electricity | 6 | Active |
| US8910168B2 | Task backpressure and deletion in a multi-flow network processor architecture | Emerging Cross-Sectional Technologies | 6 | Active |
| US8537832B2 | Exception detection and thread rescheduling in a multi-core, multi-thread network processor | Physics | 6 | Active |
| US8868889B2 | Instruction breakpoints in a multi-core, multi-thread network communications processor architecture | Electricity | 5 | Active |
| US9154442B2 | Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors | Electricity | 5 | Active |
| US8910171B2 | Thread synchronization in a multi-thread network communications processor architecture | Electricity | 5 | Active |
| US8505013B2 | Reducing data read latency in a network communications processor architecture | Electricity | 5 | Active |
| US9081742B2 | Network communications processor architecture | Electricity | 5 | Active |
| US8514874B2 | Thread synchronization in a multi-thread network communications processor architecture | Electricity | 4 | Active |
| US8539199B2 | Hash processing in a network communications processor architecture | Electricity | 4 | Active |
| US8943507B2 | Packet assembly module for multi-core, multi-thread network processors | Physics | 3 | Active |
| US6275924A | System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time | Physics | 3 | Expired |
| US8873550B2 | Task queuing in a multi-flow network processor architecture | Electricity | 1 | Active |
| US9094219B2 | Network processor having multicasting protocol | Electricity | 1 | Active |
| US8949582B2 | Changing a flow identifier of a packet in a multi-thread, multi-flow network processor | Electricity | 1 | Active |
| US8499137B2 | Memory manager for a network communications processor architecture | Electricity | 1 | Active |
| US9461930B2 | Modifying data streams without reordering in a multi-thread, multi-flow network processor | Electricity | 0 | Active |
| US11580371B2 | Method and apparatus to efficiently process and execute Artificial Intelligence operations | Physics | 0 | Active |
| US9864633B2 | Network processor having multicasting protocol | Electricity | 0 | Active |
| US8677075B2 | Memory manager for a network communications processor architecture | Electricity | 0 | Active |
| US8761204B2 | Packet assembly module for multi-core, multi-thread network processors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.