Methods and apparatus for design rule checking
US6275971A · kind A · utility
49Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.