Wafer level packaging method and packages formed
US6277669A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a wafer level package and packages formed are disclosed. In the method, an elastomeric material layer is first deposited on top of a passivation layer by a printing, coating or laminating method to form a plurality of isolated islands. The islands may have a thickness of less than 100 .mu.m. Metal traces for I/O redistribution are then formed to connect the isolated islands with bond pads provided on the surface of the wafer such that one bond pad is connected electrically to one isolated island. On top of the metal trace is then deposited an organic material for insulation with the metal trace on top of the isolated islands exposed. After an UBM layer is formed on top of the metal traces that are exposed on the isolated islands, solder balls of suitable size may be planted by a plating technique, a printing technique or a pick and place technique to complete the wafer level package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.