Method for manufacturing an SOI wafer
US6277703A · kind A · utility
21Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including: forming doped regions on a monocrystalline substrate; growing an epitaxial layer; forming trenches in the epitaxial layer extending to the doped regions; anodizing the doped regions in an electro-galvanic cell to form porous silicon regions; oxidizing the porous silicon regions; removing the oxidized porous silicon regions to form a buried air gap; thermally oxidizing the substrate to grow an oxide region from the walls of the buried air gap and the trenches, until the buried air gap and the trenches themselves are filled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.