Method for fabricating an air-gap with a hard mask
US6277705A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2000 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Jan 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method for an air-gap, in which method hard mask is used, is described. A patterned hard mask layer is formed on a semiconductor substrate. Taking advantage of the etching selectivity of the hard mask layer to the dielectric layer, an opening with a high aspect ratio is formed in the dielectric layer. A conductive plug is then formed in the opening, followed by forming a conductive layer on the hard mask layer to cover the conductive plug. The hard mask layer is further removed. A silicon oxide layer with poor step coverage is formed to cover the substrate. Using the space remaining after the removal of the hard mask layer, an air-gap is formed between the conductive layer and the dielectric layer to enhance the insulation effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.