Silicon nitride dopant diffusion barrier in integrated circuits
US6277720A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Jun 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process. The first etch selectively etches silicon dioxide relative to silicon nitride, and thus stops on silicon nitride layer (30); besides serving as an etch stop, silicon nitride layer (30) protects underlying active regions (6, 7) from damage that may be caused by ionized oxygen released during oxide etch. A brief nitride etch is then used to clear silicon nitride layer (30), without damaging comer locations (NC) of the sidewall structures (11).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.