Method for fabricating an interconnect
US6277755A · kind A · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.