Low-power flip-flop circuit employing an asymmetric differential stage
US6278308A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the "output side" and the "reference side," are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.