Multi-array memory device, and associated method, having shared decoder circuitry
US6278646A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, and an associated method, contain at least two memory arrays and a single decoder shared by the memory arrays. When data is to be accessed from selected memory locations of one of the memory arrays, the non-selected memory array is inactivated by precharging the bit lines of the array to a common voltage with the data input and/or output buses for that array, thereby allowing the decoder to select the inactive array without harm, and thereby preventing the need for additional decoder circuitry to discriminate between the arrays. The array containing the selected memory locations remains active, thereby permitting accessing of the memory locations therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.