Pipelined two-cycle branch target address cache
US6279105A · kind A · utility
30Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.