Inventor · Austin, TX, US

David S. Levitan

73Patents
16h-index
51Co-inventors
87Inventor score

Filing activity: Jan 8, 1993 → Jan 4, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US5367703A Method and system for enhanced branch history prediction accuracy in a superscalar processor system Physics 70 Expired
US5553255A Data processor with programmable levels of speculative instruction fetching and method of operation Physics 67 Expired
US7487334B2 Branch encoding before instruction cache write Physics 61 Expired
US5796758A Self-checking content-addressable memory and method of operation for detecting multiple selected word lines Electricity 53 Expired
US7809933B2 System and method for optimizing branch logic for handling hard to predict indirect branches Physics 42 Active
US7269715B2 Instruction grouping history on fetch-side dispatch group formation Physics 41 Expired
US9069563B2 Reducing store-hit-loads in an out-of-order processor Physics 32 Active
US5872950A Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages Physics 31 Expired
US6279105A Pipelined two-cycle branch target address cache Physics 30 Expired
US5758143A Method for updating a branch history table in a processor which resolves multiple branches in a single cycle Physics 27 Expired
US7032097B2 Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache Physics 25 Expired
US7657783B2 Apparatus and computer program product for testing ability to recover from cache directory errors Physics 25 Active
US6662360B1 Method and system for software control of hardware branch prediction mechanism in a data processor Physics 19 Expired
US7783870B2 Branch target address cache Physics 19 Active
US5421020A Counter register implementation for speculative execution of branch on count instructions Physics 18 Expired
US8943299B2 Operating a stack of information in an information handling system Physics 17 Active
US7120784B2 Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment Physics 16 Expired
US8131976B2 Tracking effective addresses in an out-of-order processor Physics 15 Active
US6651162B1 Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache Physics 15 Expired
US9983878B2 Branch prediction using multiple versions of history data Physics 13 Active
US8635621B2 Method and apparatus to implement software to hardware thread priority Physics 11 Active
US5918044A Apparatus and method for instruction fetching using a multi-port instruction cache directory Emerging Cross-Sectional Technologies 11 Expired
US7877586B2 Branch target address cache selectively applying a delayed hit Physics 10 Active
US7689816B2 Branch prediction with partially folded global history vector for reduced XOR operation time Physics 10 Active
US5796998A Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system Physics 10 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.