Method of on-chip interconnect design
US6279142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of on-chip interconnect design in an integrated circuit (IC) is provided. Fast circuit simulations of each net constituting the IC are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasitic cross-coupling capacitances and shunt capacitances derived from three-dimensional field solver evaluations of pre-routing phase estimated wire geometries. If the noise margin and slew rate criteria are not satisfied for the net under simulation, the simulations are iterated, with a new wire geometry selected between iterations, until the criteria are satisfied. Each net is tagged with a wire geometry that satisfies noise margin and slew rate requirements which can then be passed to a routing tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.