Howard H. Smith
24Patents
9h-index
31Co-inventors
75Inventor score
Filing activity: Apr 13, 1998 → Jul 31, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6279142A | Method of on-chip interconnect design | Physics | 29 | Expired |
| US6028989A | Calculating crosstalk voltage from IC craftsman routing data | Physics | 27 | Expired |
| US6342823B1 | System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation | Physics | 18 | Expired |
| US7093206B2 | Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures | Physics | 15 | Expired |
| US6546529B1 | Method for performing coupling analysis | Physics | 14 | Expired |
| US6418401B1 | Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation | Physics | 11 | Expired |
| US7971171B2 | Method and system for electromigration analysis on signal wiring | Physics | 11 | Active |
| US6323050A | Method for evaluating decoupling capacitor placement for VLSI chips | Physics | 11 | Expired |
| US6374394B1 | Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip | Physics | 10 | Expired |
| US6460169B1 | Routing program method for positioning unit pins in a hierarchically designed VLSI chip | Physics | 9 | Expired |
| US6415428B1 | Minimal length method for positioning unit pins in a hierarchically designed VLSI chip | Physics | 7 | Expired |
| US6618843B2 | Method for evaluating decoupling capacitor placement for VLSI chips | Physics | 5 | Expired |
| US6333680A | Method and system for characterizing coupling capacitance between integrated circuit interconnects | Physics | 4 | Expired |
| US6618844B2 | Method for evaluating decoupling capacitor placement for VLSI chips | Physics | 4 | Expired |
| US7269806B2 | Decoupling capacitance analysis method | Physics | 3 | Expired |
| US7319946B2 | Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques | Physics | 3 | Expired |
| US9582622B1 | Evaluating on-chip voltage regulation | Physics | 2 | Active |
| US7086026B2 | Decoupling capacitance analysis method | Physics | 2 | Expired |
| US9607118B1 | Evaluating on-chip voltage regulation | Physics | 1 | Active |
| US7844435B2 | Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques | Physics | 1 | Active |
| US6963204B2 | Method to include delta-I noise on chip using lossy transmission line representation for the power mesh | Electricity | 1 | Expired |
| US7346877B2 | Decoupling capacitance analysis method | Physics | 1 | Active |
| US7006931B2 | System and method for efficient analysis of transmission lines | Physics | 1 | Expired |
| US10467372B2 | Implementing automated identification of optimal sense point and sector locations in various on-chip linear voltage regulator designs | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.