Process for manufacturing a chip carrier substrate
US6280640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | May 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.