Wafer flattening process and system
US6280645A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Jun 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31056
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer flattening process and system enables a reduction of the surface roughness of a wafer resulting from local etching. A silicon wafer W is brought into close proximity to a nozzle portion 20 to feed SF.sub.6 gas to an alumina discharge tube 2, a plasma generator 1 is used to cause plasma discharge and spray a first activated species gas from the nozzle portion 20 to the silicon wafer W side, an X-Y drive mechanism 4 is used to make the nozzle portion 20 scan to perform a local etching step. Then the silicon wafer W is moved away from the nozzle portion 20 and O.sub.2 gas and CF.sub.4 gas are fed to the alumina discharge tube. At this time, the O.sub.2 gas is set to be greater in amount than the CF.sub.4 gas. When this mixed gas is made to discharge to generate plasma, a second activated species gas diffuses from the nozzle portion 20 to the entire surface of the silicon wafer W. Since there is a larger amount of O radicals than F radicals, the reaction product resulting from the O radicals deposit in fine depressions causing roughness and the front surface of the silicon wafer W is smoothed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.