Method of solder bumping a circuit component
US6281106A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Nov 25, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for solder bumping a surface-mount circuit component, as well as electrically and mechanically connecting the component to a conductor on a substrate, and the components and assemblies formed thereby. The method generally entails forming a multilayer metal bump containing discrete layers, including at least one layer of a solder alloy, a first metallic layer having a sufficiently high melting point so as not to melt or deform at the reflow temperature of the solder alloy, and a second metallic layer containing at least one metal that is soluble in the solder alloy. During reflow, the first metallic layer does not collapse, while the solder layer and the second metallic layer readily flow and subsequently bond the first metallic layer to suitable structures on the component and substrate. As a result of the reflow operation, the multilayer metal bump of this invention forms a solder connection with a graded composition, namely, an intermediate region formed primarily by the first metallic layer, and at least one end region that contains a solid solution formed of the solder layer and the first and second metallic layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.