Wafer carrier modification for reduced extraction force
US6281128A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Jun 14, 2019 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B37/30
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
The present invention provides a wafer carrier for use with a semiconductor wafer polishing apparatus. In one embodiment, the wafer carrier comprises a carrying head having opposing first and second surfaces, a primary channel system formed in the second surface, and a secondary channel system formed in the second surface. The first surface is coupleable to the semiconductor polishing apparatus and the second surface is adapted to receive a semiconductor wafer to be polished. The primary channel system comprises first and second intersecting channels. The secondary channel system intersects the primary channel system so that the secondary channel system and the primary channel system cooperate to occupy a substantial portion of a surface area of the second surface. Therefore, the primary channel system and the secondary channel system decrease an amount of force required to remove the semiconductor wafer from the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.