Insulated gate field effect transistor and manufacturing method of the same
US6281546A · kind A · utility
4Cited by
2References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
Abstract
A wide high concentration P.sup.+ type region is formed on the surface of an N.sup.- type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, holes generated at the outside of the cell region mostly flow through the P.sup.+ type region and reach to an emitter electrode. Therefore, the flow amount of the holes does not concentrate on a channel P well for forming a channel region of the transistor device at the cell edge portion, whereby a ruggedness against a latch-up phenomenon can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.