Patent · US Expired

Chips arranged in plurality of planes and electrically connected to one another

US6281577A · kind A · utility

240Cited by

17References

7Claims

0Family size

Assignee

Pac Tech—Packaging Technologies Gmbh · DE

Inventors

Hans-Hermann Oppermann · Berlin, DE
Elke Zakel · Falkensee, DE
Ghassem Azdasht · Berlin, DE
Paul Kasulke · Berlin, DE

Key dates

Filing date	Apr 22, 1997
Grant date	Aug 28, 2001
Priority date	—
Expiry date	Apr 22, 2017

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged either transverse to the longitudinal extent of the carrier substrate or parallel to the longitudinal extent of the flexibly constructed carrier substrate, as well as a spatial chip arrangement that is formed by means of this process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.