Package structure for semiconductor chip
US6281592A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Mar 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01087
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure for a semiconductor chip, comprising: a resin substrate having pads formed thereon, a semiconductor chip having electrodes connected to the pads through bumps, an underfiller filling a space between the semiconductor chip and the resin substrate and bonding the semiconductor chip to the resin substrate, and a stiffener or an elastomer buried in the resin substrate in a portion underneath the semiconductor chip to mitigate or absorb a thermal stress acting between the semiconductor chip, the underfiller and the resin substrate, thereby preventing upward depression of the lower surface of the substrate in a portion underneath the semiconductor chip or preventing fracture of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.