Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
US6281726A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2000 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Mar 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor. A second multiplexer then selects and outputs the second output clock from among the second series of delayed clocks in accordance with the second count. As a result, at least one of the clocks is generated with improved resolution over convent…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.