Low consumption ROM
US6282114A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2000 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | May 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.