Memory test method and nonvolatile memory with low error masking probability
US6282134A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device has a signature code generator generating a present signature code from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address of a memory cell being addressed; in this case the output of the code generator is a function of data read from the cell array, the previously calculated signature code and the address of the read data. The data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code varies in dynamic way; at the end of memory scanning, the signature code is compared to an expected result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.