Promod Kumar
31Patents
9h-index
29Co-inventors
75Inventor score
Filing activity: Oct 4, 1996 → Oct 12, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6587913B2 | Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode | Physics | 78 | Expired |
| US6470431B2 | Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data | Physics | 69 | Expired |
| US6624679B2 | Stabilized delay circuit | Physics | 43 | Expired |
| US6452864B1 | Interleaved memory device for sequential access synchronous reading with simplified address counters | Physics | 26 | Expired |
| US6473339B2 | Redundancy architecture for an interleaved memory | Physics | 26 | Expired |
| US7050343B2 | Built-in testing methodology in flash memory | Physics | 16 | Expired |
| US6282134A | Memory test method and nonvolatile memory with low error masking probability | Physics | 15 | Expired |
| US8218377B2 | Fail-safe high speed level shifter for wide supply voltage range | Physics | 15 | Active |
| US8154335B2 | Fail safe adaptive voltage/frequency system | Emerging Cross-Sectional Technologies | 9 | Active |
| US6438048B1 | Nonvolatile memory and high speed memory test method | Physics | 8 | Expired |
| US6487140B2 | Circuit for managing the transfer of data streams from a plurality of sources within a system | Physics | 4 | Expired |
| US8269545B2 | Fail safe adaptive voltage/frequency system | Emerging Cross-Sectional Technologies | 4 | Active |
| US6625706B2 | ATD generation in a synchronous memory | Physics | 2 | Expired |
| US7750689B1 | High voltage switch with reduced voltage stress at output stage | Electricity | 2 | Active |
| US11984151B2 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US6638818B1 | Method of fabricating a dynamic random access memory with increased capacitance | Emerging Cross-Sectional Technologies | 1 | Expired |
| US6366634B2 | Accelerated carry generation | Physics | 1 | Expired |
| US12087356B2 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US12170120B2 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Physics | 0 | Active |
| US12159689B2 | SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications | Physics | 0 | Active |
| US12237007B2 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12046324B2 | Modular memory architecture with gated sub-array operation dependent on stored data content | Physics | 0 | Active |
| US12183424B2 | Bit-cell architecture based in-memory compute | Physics | 0 | Active |
| US12176025B2 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12361982B2 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.