Multi-port static random access memory design for column interleaved arrays
US6282143A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | May 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random-access memory (SRAM) comprises multi-port storage cells with built-in column-interleave selection circuitry which allow a storage cell to be written to via a plurality of different write paths. Column selects are built into each storage cell by adding an additional isolating switch between the storage node of the storage cell and the bitline of a particular write path in order to prevent a cell write from affecting other storage cells connected to the same wordline in the same interleaved array. The write data bus corresponding to each write path for all interleaved cells are shared by all storage cells in a common interleave group, and each adjacent pair of storage cells in a common row share bitlines coupled to the common data bus, resulting in smaller number of required bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.